LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--Circuitos Logicos com 4 portas de 2 entradas

ENTITY ic_1 IS

    PORT(pin1, pin2, pin4, pin5, pin9, pin10, pin12, pin13: IN STD_LOGIC; 
        pin3, pin6, pin8, pin11: OUT STD_LOGIC);

END ic_1;

ARCHITECTURE and_ic OF ic_1 IS

BEGIN

    pin3 <= pin1 AND pin2;
    pin6 <= pin4 AND pin5;
    pin8 <= pin9 AND pin10;
    pin11 <= pin12 AND pin13;

END and_ic;

ARCHITECTURE or_ic OF ic_1 IS

BEGIN

    pin3 <= pin1 OR pin2;
    pin6 <= pin4 OR pin5;
    pin8 <= pin9 OR pin10;
    pin11 <= pin12 OR pin13;

END or_ic;

ARCHITECTURE nand_ic OF ic_1 IS

BEGIN

    pin3 <= pin1 NAND pin2;
    pin6 <= pin4 NAND pin5;
    pin8 <= pin9 NAND pin10;
    pin11 <= pin12 NAND pin13;

END nand_ic;

ARCHITECTURE xor_ic OF ic_1 IS

BEGIN

    pin3 <= pin1 XOR pin2;
    pin6 <= pin4 XOR pin5;
    pin8 <= pin9 XOR pin10;
    pin11 <= pin12 XOR pin13;

END xor_ic;
